1. Field of the Invention
The invention generally relates to arrangements for suppressing digital-to-analog converter (DAC) error, especially at high frequencies. More particularly, the invention relates to arrangements for suppressing DAC error using dynamic averaging techniques.
2. Related Art
Sigma delta modulators (SDMs) are used in data converters, such as analog-to-digital converters (ADCs), in which the SDM performs noise shaping functions. SDMs may be first order, second order, or n-th order, where n is a positive integer.
A typical first order SDM includes a filter (such as an integrator circuit) and a quantizer (such as a flash ADC). The filter receives an analog input signal as well as a feedback signal. The quantizer quantizes the filter output signal to create a digital output. In its simplest form, the quantizer may be a single bit ADC such as a comparator circuit.
A digital to analog converter (DAC) creates an analog representation of the SDM's current digital output. The DAC provides this analog representation as an analog feedback signal to the filter. Multiple order sigma delta modulators may include a series of filters in a forward path, each filtering the output of the previous filter and receiving an analog feedback signal based on a digitized output of the modulator. The first filter operates on the analog input signal to be converted and a feedback signal.
Multi-bit or multi-level sigma delta modulators (SDMs) provide multi-bit digital or quantized outputs, in which the ADC provides a multi-bit digital output representative of the input signal. In this case, the feedback DAC is a multi-bit converter as well.
Whereas single-bit SDMs can achieve good linearity, noise performance and stability are generally not as good as in multi-bit sigma delta modulators. The linearity of a multi-bit SDM is essentially limited by the linearity of the DAC, particularly nonlinearity due to mismatch of internal DAC components that causes distortion in the modulator. This distortion typically manifests as harmonics of the input signal, which is a serious problem for applications such as audio data conversion.
One approach for dealing with the non-linearity problems for multi-bit data converters involves dynamic element matching (DEM). DEM transforms the non-linearity error caused by DAC element mismatch into shaped noise. DEM also noise-shapes by changing the bit pattern of data such that most of the noise falls outside the signal band of interest. This out-of-band noise can then be filtered out, for example, by decimation filtering.
In general, DAC element mismatch is thus converted from a static error into wide-bandwidth noise by selecting different DAC elements to represent a digital input code at different times. Such DEM techniques may be employed in an SDM feedback path to vary the selection of mismatched components in the DAC in response to the quantized (e.g., digital input) signal.
Data weighted averaging (DWA) is one example of a DEM algorithm. However, DWA suffers from the production of unintended tone components in the output, sometimes referred to as idle channel tones. This problem is particularly troublesome for static (DC) or slowly changing input signals, and/or for low oversampling ratios (e.g., less than or equal to 8). In such situations, the modulator creates a repetitive pattern that manifests as a tonal component in the output spectrum. This degrades usable system range, which is sometimes measured as spurious free dynamic range (SFDR).
In a simple example, a digital-to-analog converter (DAC) has only two input bits. In this two-input-bit DAC, DAC output elements are provided in a four-bit word whose component bits are referred to herein as e1, e2, e3 and e4 (see examples in FIGS. 1–5). If the DAC has, for example, an input sequence 01, 10, 11, 11 (that is, 1, 2, 3, 3 as shown in FIGS. 1–5), and if a conventional “thermometer code” is used, the thermometer code sequence is 0001, 0011, 0111, 0111. If a bit is 1, its corresponding output element is activated.
In the conventional arrangement shown in FIG. 1, for example, “1” bits are shifted in from the “bottom” of the charts, based on successive values in the input sequence. The corresponding thermometer code 0001, 0011, 0111, 0111 can be read vertically in the columns in FIG. 1.
Dynamic element matching (DEM) techniques have been used to suppress DAC error in oversampling systems. However, conventional approaches generally produce either white noise or a high pass profiles DAC error.
With the conventional DAC conversion scheme shown in FIG. 1, a predetermined fixed set of DAC elements corresponds to each input code. Undesirably, harmonic distortion components due to element mismatch are generated, and spurious free dynamic range (SFDR) is therefore limited.
A first class of algorithms to improve spurious free dynamic range (SFDR) is random averaging (see FIG. 2 for an example). Random averaging involves randomly assigning elements from all available elements for each individual digital input to the DAC. As a result, DAC error is averaged out throughout the bandwidth and the error is converted to resemble white noise, as shown in the error distribution graph of FIG. 2.
Another class of algorithms involves converting DAC error into high pass noise (see FIG. 3 for an example). In such algorithms as DWA, DAC elements are chosen sequentially for each incoming digital code, with a direction of either single or multiple pointers. In FIG. 3, dots point to the location of the next shifting operation; the elements after the pointer are used for D/A conversion during a following clock cycle. As a result of the shifting operation, the DAC error due to element mismatch is averaged out at low frequency and only allowed to pass at high frequency. Accordingly, the error distribution is a high-pass distribution, as shown in the bottom panel of FIG. 3.
FIG. 4 shows an arrangement following the disclosure of I. Fujimori, L. Longo, A. Hairapetian, K. Seiyama, S. Kosic, J. Cao and S. Chan, “A 90 dB SNR, 2.5 MHz Output Rate ADC using Cascaded Delta Sigma Modulation at 8× Oversampling Ratio,” 2000 IEEE International Solid-State Circuits Conference (ISSCC), pp. 338–339 (2000). Fujimori's approach, although involving bidirectional data weighted averaging, still results in a high-pass error distribution that resembles that of FIG. 3. Also, significantly, Fujimori's approach involves two independent pointers in order to govern shifting in two directions, which adds to complexity of the design.
Accordingly, there is a need in the art to provide suppression of DAC error, especially at high frequencies around half the sampling frequency, so that a low pass error distribution profile is presented.